The invention is in the field of transistor amplifier circuits and relates more particularly to cascode amplifier circuits suitable for use in such applications as rf power amplification.
Cascode amplifiers are used in wireless communications apparatus and other rf amplifier applications due to their increased output resistance and reduced unwanted capacitive feedback. However, typical conventional cascode amplifiers require the use of two bias circuits, one for the common-emitter (or source) transistor and the other for the common-base (or gate) transistor (depending upon whether bipolar or FET transistors are used).
Cascode amplifier circuits have sought to overcome this disadvantage using either a resistive network, as shown in U.S. Pat. No. 5,488,382, or else have provided a gate bias to the common-gate transistor by a direct connection to a power supply terminal, as shown in U.S. Pat. No. 6,292,060. However, these prior-art solutions are not optimum in that additional resistors usually require greater chip area than do active devices, and in that obtaining a control electrode bias directly from the power supply voltage puts operational limitations on the amplifier.
Accordingly, it would be desirable to have a self-biased cascade amplifier circuit in which the use of resistor networks to obtain bias signals is minimized, and in which operational flexibility is obtained by not supplying the bias voltage directly from the power supply.
Objects of the invention are therefore to provide a self-biased cascode amplifier circuit in which no external bias supplies are used, the use of resistor networks is minimized, and operational flexibility is achieved by not providing a bias voltage directly from the power supply, thus realizing a simple, compact, efficient and economical circuit.
In accordance with the invention, these objects are achieved by a new self-biased cascode amplifier circuit having first and second transistors connected in series and coupled between a dc voltage source terminal and a common terminal, with an input signal terminal being coupled to a control electrode of the first transistor and an output signal terminal coupled to an output terminal of the second transistor. An integrated bias circuit is coupled between the dc voltage source terminal and the common terminal for internally biasing both the first and the second transistors without the use of an external bias supply or a direct bias connection to the dc voltage source.
In a preferred embodiment on the invention, the integrated bias circuit includes third and fourth transistors connected in series and coupled between the dc voltage source terminal and the common terminal.
In a further preferred embodiment of the invention, a control electrode of the third transistor is coupled to the control electrode of the first transistor to form a current mirror.
A fully self-biased cascode amplifier in accordance with the present invention offers significant advantages over prior-art circuits in that no external bias supplies are required, the use of resistor networks is minimized, and greater operational flexibility is obtained by not using the power supply voltage as a direct source of bias voltage.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.